Programmable Structured ASIC Technology
Programmable Structured ASIC technology reduces the costs and risks of
designing chips without the circuit performance and unit cost penalties
or design size limitations normally associated with providing
reconfigurability in a chip.
Designers and producers of integrated electronic circuits worldwide are
currently forced to make trade-offs between an economic, technically
easier, low-risk and faster-to-market design approach using
reconfigurable technologies such as Field Programmable Gate Arrays
(FPGAs), and the higher performance, lower power, larger design-size
capacity and lower unit costs normally only achieveable by designing a
traditional, customised Application Specific Integrated Circuit-based
(ASIC) product. The ASIC approach, which may involve a fully-customised
or a semi-custom “structured ASIC” involves expensive and
time-consuming customer-specific production steps to produce working
prototypes.
Spangaro Systems’ Programmable Structured ASIC technology is
different. The technology brings the best of both the FPGA and ASIC
worlds without the compromises usually associated with either. This
positioning is represented in the inset figure.
Using Programmable Structured ASIC technology, designers can design
low-cost, high-performance chips with a prototyping
“reprogrammable version” of their chip. Hardware designs
may be compiled, downloaded, run and debugged in the real hardware
prototype at the desktop. When hardware and other software and systems
engineers are happy with the implementation, conversion to a low-cost,
fixed “production version” is performed using an economic,
straightforward process that preserves the integrity of the original
design.
Compare this to existing solutions which must sacrifice either true
desktop reconfigurability (instead requiring production runs to
prototype a design), incur significant built-in cost and performance
overheads for reconfigurability, or involve complex, expensive and
difficult conversion processes and are anyway unable to match ASIC-like
design-size capacities. Hence the unsatisfactory need to make trade-off
decisions about which is the “lesser evil”.
The problem is only getting worse, and is causing a drag on the entire
semiconductor industry. As companies chase performance to remain
competitive, the costs of developing chips with new sub-micron
technologies are increasing exponentially. A step-function breakthrough
in the approach to semiconductor design is needed to enable companies
to meet time-to-market and cost/volume targets in the future. The
Programmable Structured ASIC delivers this solution to the US$18b ASIC
and US$3b FPGA markets.
Together with our technology partners, Spangaro Systems will change the
face of semiconductor design. Our vision is Everybody Gets
Reconfigurability. Our technology brings a sigh of relief to
semiconductor companies and Wall Street analysts alike who worry about
nothing more than the impending challenge of meeting today’s and
tomorrows design costs and managing the substantial risks of
semiconductor product development.
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